Test Synthesis Welcome to the home page of the Test Synthesis project at the Embedded Systems Laboratory (ESLAB) of the Department of Computer and Information Science (IDA), Linköping University. Project Description The main objective of this project is to develop systematic techniques to integrate testability consideration into high-level synthesis. We are developing algorithms to predict testability of the synthesized circuits accurately in the early stage and optimize the designs in terms of test cost as well as performance and area cost. One technique we have developed is a high-level test synthesis algorithm for operation scheduling, data path allocation, and scan register selection. Data path allocation is achieved by a controllability/observability balance allocation technique which is based on testability analysis at register-transfer level. Scheduling, on other hand, is carried out by rescheduling transformations which change the default scheduling to improve testability. At the same time, analysis is carried out to avoid generating loops as much as possible during the high-level synthesis process. Additionally, scan register selection is performed based also on testability analysis. All the techniques are integrated together in a transofmrational approach to high-level synthesis. Contrary to other works in which scheduling, allocation and scan register selection are performed independently, our approach integrates these tasks by performing them simultaneously. In this way, the effects of scheduling, allocation and scan register selection on testability during the high-level synthesis are exploited more effectively. Project Members Zebo Peng (contact person, zebpe@ida.liu.se) Tianruo Yang Selected Publications The following publications are available as postscript files: Tianruo Yang and Zebo Peng: Integrated Scheduling and Allocation in High-Level Test Synthesis, Proceedings of The IEEE European Test Workshop (ETW-97), Cagliari, Italy, 1997. Tianruo Yang and Zebo Peng : An Integrated Approach to Data Path Synthesis for Testability, Fourth International Test Synthesis Workshop (ITSW-97), Santa Barbara, USA, 1997. Zebo Peng: High-Level Test Synthesis Using Design Transformations, Second International Test Synthesis Workshop (ITSW-95), Santa Barbara, USA, May 8-10, 1995.