*
* BER (Blom-Egelnor-Rydell) high-speed serial hardware
* $VER: ber.i 1.0 (12.5.97)
*
* Rätt fult filhuvud!
*
IFND EXEC_TYPES_I
INCLUDE exec/types.i
ENDC
*** Hardware register map
STRUCTURE BERREGISTERS,0
UBYTE ber_Pad0
LABEL ber_dll ; Divisor Latch LSB
LABEL ber_rhr ; Receive Holding Register
UBYTE ber_thr ; Transmit Holding Register
UBYTE ber_Pad1
LABEL ber_dlm ; Divisor Latch MSB
UBYTE ber_ier ; Interrupt Enable Register
UBYTE ber_Pad2
LABEL ber_fcr ; FIFO Control Register
UBYTE ber_isr ; Interrupt Status Register
UBYTE ber_Pad3
UBYTE ber_lcr ; Line Control Register
UBYTE ber_Pad4
UBYTE ber_mcr ; Modem Control Register
UBYTE ber_Pad5
UBYTE ber_lsr ; Line Status Register
UBYTE ber_Pad6
UBYTE ber_msr ; Modem Status Register
UBYTE ber_Pad7
UBYTE ber_spr ; ScratchPad Register
LABEL ber_SIZEOF
*** IER bits
BITDEF BERIER,RXENA,0 ; Receive interrupt enable
BITDEF BERIER,TXENA,1 ; Transmit interrupt enable
BITDEF BERIER,LSENA,2 ; Line status interrupt enable
BITDEF BERIER,MSENA,3 ; Modem status interrupt enable
*** ISR bits
BITDEF BERISR,NOIRQ,0 ; Interrupt pending
BITDEF BERISR,FIFOMODE,7 ; 16450/16550 mode
BERISRF_MSR EQU %000 ; Modem status interrupt pending
BERISRF_TXRDY EQU %010 ; Transmit interrupt pending
BERISRF_RXRDY EQU %100 ; Receive interrupt pending
BERISRF_LSR EQU %110 ; Line control interrupt pending
BERISRF_MASK EQU %111
*** FCR bits
BITDEF BERFCR,FIFOENA,0 ; FIFO enable
BITDEF BERFCR,RXCLR,1 ; Clear receive FIFO
BITDEF BERFCR,TXCLR,2 ; Clear transmit FIFO
BITDEF BERFCR,XRDYHIGH,3 ; Set RXRDY/TXRDY in mode "1"
BERFCRF_TRG01 EQU %00000000 ; FIFO interrupt at 1
BERFCRF_TRG04 EQU %01000000 ; FIFO interrupt at 4
BERFCRF_TRG08 EQU %10000000 ; FIFO interrupt at 8
BERFCRF_TRG14 EQU %11000000 ; FIFO interrupt at 14
*** LCR bits
BERLCRF_LEN5 EQU %00 ; 5 data bits
BERLCRF_LEN6 EQU %01 ; 6 data bits
BERLCRF_LEN7 EQU %10 ; 7 data bits
BERLCRF_LEN8 EQU %11 ; 8 data bits
BITDEF BERLCR,LONGSTOP,2 ; 1.5 or 2 stop bits
BITDEF BERLCR,PARITYENA,3 ; Enable parity checking
BITDEF BERLCR,PARITYEVEN,4 ; Set even parity
BITDEF BERLCR,PARITYFORCED,5 ; Force parity
BITDEF BERLCR,BREAK,6 ; Send break
BITDEF BERLCR,DLABENA,7 ; Enable divisor latch registers
*** MCR bits
BITDEF BERMCR,DTR,0 ; DTR control
BITDEF BERMCR,RTS,1 ; RTS control
BITDEF BERMCR,OP1,2 ; OP1 control
BITDEF BERMCR,OP2,3 ; OP2 control
BITDEF BERMCR,DIAG,4 ; Enable loop-back diagnostics
*** LSR bits
BITDEF BERLSR,RX,0 ; Receive hoding reg. non-empty
BITDEF BERLSR,OVERRUN,1 ; Received data overrun error
BITDEF BERLSR,PARITY,2 ; Parity error
BITDEF BERLSR,FRAME,3 ; Framing error
BITDEF BERLSR,BREAK,4 ; Break signal detected
BITDEF BERLSR,THREMPTY,5 ; Transmit Holding Reg. or FIFO empty
BITDEF BERLSR,FIFOEMPTY,6 ; FIFO empty
BITDEF BERLSR,ERROR,7 ; Parity or framing error or break
*** MSR bits
BITDEF BERMSR,CTSCHG,0 ; CTS has changed state
BITDEF BERMSR,DSRCHG,1 ; DSR has changed state
BITDEF BERMSR,RICHG,2 ; RI has changed state
BITDEF BERMSR,CDCHG,3 ; CD has changed state
BITDEF BERMSR,CTS,4 ; CTS state
BITDEF BERMSR,DSR,5 ; DSR state
BITDEF BERMSR,RI,6 ; RI state
BITDEF BERMSR,CD,7 ; CD state
*** AutoConfig constants
BER_MANUID EQU 2011 ; Hacker-ID!
BER_PRODID EQU 162 ; Nibble-swapped 42!
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