PAL-kretsen

`ac-pal.abl' är Abel-programmet som ligger i PAL-kretsen, U10.

MODULE ACPAL

TITLE 'Autoconfig PAL'

"INPUTS
!asq, !asqq, rd, !bdsel, !berr, !res		pin 1,2,3,4,5,6;
a1, a2, a3, a4, a5, a6				pin 7,8,9,10,11,13;

"OUTPUTS
!dboe, !wp, !oe, !shutup, !precon, !conout	pin 14,15,16,17,18,19 ISTYPE 'COM';
bd12, bd13, bd14, bd15				pin 20,21,22,23 ISTYPE 'COM';

EQUATIONS   "*** Kontrollsignaler ***

" Enable data buffers
dboe	= (!res & bdsel & !berr & !shutup & !rd) #
	  (!res & bdsel & !berr & !shutup & rd & asq);

" ST16550 Write pulse
wp	= !res & asq & asqq & bdsel & conout & !shutup & !berr & !rd;

" ST16550 Output Enable/Read
oe	= !res & asq & bdsel & conout & !berr & rd;

" If we're told to shut up, shut up until reset
shutup	= (!res & bdsel & !rd & asq & !conout &
	    ([a6..a2,0,0] == ^h4C)) #
	  (!res & shutup );

" When we have got out base address, set precon
precon	= (!res & shutup) #
	  (!res & !rd & bdsel & asqq & ([a6..a1,0] == ^h48)) #
	  (!res & precon);

" When precon goes active, pass the config signal to next Zorro board
conout	= (!res & !asq & precon) #
	  (!res & conout);

"*** Autoconfig ROM ***

bd12.OE	= !res & bdsel & !conout & rd & !berr & !shutup;
bd13.OE	= !res & bdsel & !conout & rd & !berr & !shutup;
bd14.OE	= !res & bdsel & !conout & rd & !berr & !shutup;
bd15.OE	= !res & bdsel & !conout & rd & !berr & !shutup;

TRUTH_TABLE
	([a6..a1,.x.] -> [!bd15,!bd14,!bd13,!bd12])
	^h00 -> [!1,!1,!0,!0];	"Z2, no mem, no ROM (not inverted!)
	^h02 -> [!0,!0,!0,!1];	"Not chained, 64 KB (not inverted!)
	^h04 -> ^ha;		"Product ID High
	^h06 -> ^h2;		"Product ID Low
	^h08 -> [0,0,0,0];	"Any space, can shutup
	^h0A -> [0,0,0,0];	"Reserved
	^h0C -> 0;		"Reserved
	^h0E -> 0;		"Reserved
	^h10 -> ^h0;		"Manufacturer ID High
	^h12 -> ^h7;		"Manufacturer ID
	^h14 -> ^hd;		"Manufacturer ID
	^h16 -> ^hb;		"Manufacturer ID Low
	^h18 -> ^h0;		"Serial number High
	^h1A -> ^h0;		"Serial number
	^h1C -> ^h0;		"Serial number
	^h1E -> ^h0;		"Serial number
	^h20 -> ^h0;		"Serial number
	^h22 -> ^h0;		"Serial number
	^h24 -> ^h0;		"Serial number
	^h26 -> ^h1;		"Serial number Low
	^h28 -> ^h0;		"ROM vector High
	^h2A -> ^h0;		"ROM vector
	^h2C -> ^h0;		"ROM vector
	^h2E -> ^h0;		"ROM vector Low
	^h30 -> 0;		"Reserved
	^h32 -> 0;		"Reserved
	^h34 -> 0;		"Reserved
	^h36 -> 0;		"Reserved
	^h38 -> 0;		"Reserved
	^h3A -> 0;		"Reserved
	^h3C -> 0;		"Reserved
	^h3E -> 0;		"Reserved
	^h40 -> [!0,!0,!0,!0];	"No INT, no INT7, INT6 or INT2 (not inverted!)
	^h42 -> [!0,!0,!0,!0];	"No interrupt enable (not inverted!)
	^h44 -> 0;		"Reserved
	^h46 -> 0;		"Reserved
	^h48 -> 0;		"Base address High (Write-only)
	^h4A -> 0;		"Base address Low (Write-only)
	^h4C -> 0;		"Shutup, trigger (Write-only)
	^h4E -> 0;		"Shutup, ignored (Write-only)
	^h50 -> 0;		"Reserved
	^h52 -> 0;		"Reserved
	^h54 -> 0;		"Reserved
	^h56 -> 0;		"Reserved
	^h58 -> 0;		"Reserved
	^h5A -> 0;		"Reserved
	^h5C -> 0;		"Reserved
	^h5E -> 0;		"Reserved
	^h60 -> 0;		"Reserved
	^h62 -> 0;		"Reserved
	^h64 -> 0;		"Reserved
	^h66 -> 0;		"Reserved
	^h68 -> 0;		"Reserved
	^h6A -> 0;		"Reserved
	^h6C -> 0;		"Reserved
	^h6E -> 0;		"Reserved
	^h70 -> 0;		"Reserved
	^h72 -> 0;		"Reserved
	^h74 -> 0;		"Reserved
	^h76 -> 0;		"Reserved
	^h78 -> 0;		"Reserved
	^h7A -> 0;		"Reserved
	^h7C -> 0;		"Reserved
	^h7E -> 0;		"Reserved

TEST_VECTORS
	([shutup,res,bdsel,rd,asq,conout,a6,a5,a4,a3,a2,a1] ->
	  [shutup])
	[0,0,1,0,1,0, 1,0,0,1,1,.x.] -> [1];
	[1,0,.x.,.x.,.x.,.x.,   .x.,.x.,.x.,.x.,.x.,.x.] -> [1];
	[.x.,1,.x.,.x.,.x.,.x., .x.,.x.,.x.,.x.,.x.,.x.] -> [0];

TEST_VECTORS
" <!res & bdsel & !conout & rd & !berr & !shutup .x. .x.> => ^h50
	([res,bdsel,conout,rd,berr,shutup,.x.,.x.,
	  .x.,a6,a5,a4,a3,a2,a1,.x.] -> [bd15..bd12])
	^h5000 -> [1,1,0,0];
	^h5002 -> [0,0,0,1];
	^h5004 -> [1,1,1,1];
	^h5006 -> [1,0,0,1];
	^h5040 -> [0,0,0,0];
	^h5042 -> [0,0,0,0];
" Everything else should be ^b1111:
	[0,1,0,1,0,0,.x.,.x., .x.,0,.x.,.x.,1,.x.,.x.,.x.] -> [1,1,1,1];
	[0,1,0,1,0,0,.x.,.x., .x.,0,.x.,1,.x.,.x.,.x.,.x.] -> [1,1,1,1];
	[0,1,0,1,0,0,.x.,.x., .x.,0,1,.x.,.x.,.x.,.x.,.x.] -> [1,1,1,1];
	[0,1,0,1,0,0,.x.,.x., .x.,1,.x.,.x.,.x.,1,.x.,.x.] -> [1,1,1,1];
	[0,1,0,1,0,0,.x.,.x., .x.,1,.x.,.x.,1,.x.,.x.,.x.] -> [1,1,1,1];
	[0,1,0,1,0,0,.x.,.x., .x.,1,.x.,1,.x.,.x.,.x.,.x.] -> [1,1,1,1];
	[0,1,0,1,0,0,.x.,.x., .x.,1,1,.x.,.x.,.x.,.x.,.x.] -> [1,1,1,1];
END

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