| Periph ID AIC | Symbol | Description |
|---|---|---|
| 1 | (AT91C_ID_SYS) | System Controller |
| Function | Description |
|---|---|
| AT91F_RSTC_CfgPMC | Enable Peripheral clock in PMC for RSTC |
| Offset | Field | Description |
|---|---|---|
| 0x0 | RSTC_RCR | Reset Control Register |
| 0x4 | RSTC_RSR | Reset Status Register |
| 0x8 | RSTC_RMR | Reset Mode Register |
| Function | Description |
|---|---|
| AT91F_RSTSoftReset | Start Software Reset |
| AT91F_RSTSetMode | Set Reset Mode |
| AT91F_RSTIsSoftRstActive | Return !=0 if software reset is still not completed |
| AT91F_RSTGetStatus | Get Reset Status |
| AT91F_RSTGetMode | Get Reset Mode |
| Offset | Name | Description |
|---|---|---|
| 0 | RSTC_PROCRST AT91C_RSTC_PROCRST | Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. |
| 1 | RSTC_ICERST AT91C_RSTC_ICERST | ICE Interface Reset 0 = No effect. 1 = If KEY is correct, resets the processor's ICE Interface. |
| 2 | RSTC_PERRST AT91C_RSTC_PERRST | Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. |
| 3 | RSTC_EXTRST AT91C_RSTC_EXTRST | External Reset 0 = No effect. 1 = If KEY is correct, asserts the NRST pin. |
| 31..24 | RSTC_KEY AT91C_RSTC_KEY | Password Should be written at value 0xA5. Writting any other value in this field aborts the write operation. |
| Offset | Name | Description | ||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | RSTC_URSTS AT91C_RSTC_URSTS | User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_RSR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_RSR. | ||||||||||||||||||
| 10..8 | RSTC_RSTTYP AT91C_RSTC_RSTTYP | Reset Type Reports the cause of the last processor reset.
| ||||||||||||||||||
| 16 | RSTC_NRSTL AT91C_RSTC_NRSTL | NRST pin level Registers the NRST level. | ||||||||||||||||||
| 17 | RSTC_SRCMP AT91C_RSTC_SRCMP | Software Reset Command in Progress. 0 = No software command is being performed. The reset controller is ready for a software command. 1 = A software reset command is being performed by the reset controller, the reset controller is busy. |
| Offset | Name | Description |
|---|---|---|
| 0 | RSTC_URSTEN AT91C_RSTC_URSTEN | User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST does not generate a User Reset. |
| 4 | RSTC_URSTIEN AT91C_RSTC_URSTIEN | User Reset Interrupt Enable 0 = USRTS bit in RSTC_RSR at 1 has no effect on SCIRQ. 1 = USRTS bit in RSTC_RSR at 1 asserts SCIRQ. |
| 11..8 | RSTC_ERSTL AT91C_RSTC_ERSTL | User Reset Enable The external reset is asserted during a time of 2 power (ERSTL+1). This allows assertion duration to be programmed between 60us and 2s. |
| 31..24 | RSTC_KEY AT91C_RSTC_KEY | Password Should be written at value 0xA5. Writting any other value in this field aborts the write operation. |