| Periph ID AIC | Symbol | Description |
|---|---|---|
| 17 | (AT91C_ID_TC0) | Timer Counter 0 |
| Signal | Symbol | PIO controller | Description |
|---|---|---|---|
| TIOA0 | (AT91C_PC19_TIOA0 ) | PIOC Periph: B Bit: 19 | Timer Counter 0 Multipurpose Timer I/O Pin A |
| TIOB0 | (AT91C_PC20_TIOB0 ) | PIOC Periph: B Bit: 20 | Timer Counter 0 Multipurpose Timer I/O Pin B |
| TCLK0 | (AT91C_PC16_TCLK0 ) | PIOC Periph: B Bit: 16 | Timer Counter 0 external clock input |
| Function | Description |
|---|---|
| AT91F_TC0_CfgPIO | Configure PIO controllers to drive TC0 signals |
| AT91F_TC0_CfgPMC | Enable Peripheral clock in PMC for TC0 |
| Periph ID AIC | Symbol | Description |
|---|---|---|
| 18 | (AT91C_ID_TC1) | Timer Counter 1 |
| Signal | Symbol | PIO controller | Description |
|---|---|---|---|
| TIOA1 | (AT91C_PC21_TIOA1 ) | PIOC Periph: B Bit: 21 | Timer Counter 1 Multipurpose Timer I/O Pin A |
| TIOB1 | (AT91C_PC22_TIOB1 ) | PIOC Periph: B Bit: 22 | Timer Counter 1 Multipurpose Timer I/O Pin B |
| TCLK1 | (AT91C_PC17_TCLK1 ) | PIOC Periph: B Bit: 17 | Timer Counter 1 external clock input |
| Function | Description |
|---|---|
| AT91F_TC1_CfgPIO | Configure PIO controllers to drive TC1 signals |
| AT91F_TC1_CfgPMC | Enable Peripheral clock in PMC for TC1 |
| Periph ID AIC | Symbol | Description |
|---|---|---|
| 19 | (AT91C_ID_TC2) | Timer Counter 2 |
| Signal | Symbol | PIO controller | Description |
|---|---|---|---|
| TIOA2 | (AT91C_PC23_TIOA2 ) | PIOC Periph: B Bit: 23 | Timer Counter 2 Multipurpose Timer I/O Pin A |
| TIOB2 | (AT91C_PC24_TIOB2 ) | PIOC Periph: B Bit: 24 | Timer Counter 2 Multipurpose Timer I/O Pin B |
| TCLK2 | (AT91C_PC18_TCLK2 ) | PIOC Periph: B Bit: 18 | Timer Counter 2 external clock input |
| Function | Description |
|---|---|
| AT91F_TC2_CfgPIO | Configure PIO controllers to drive TC2 signals |
| AT91F_TC2_CfgPMC | Enable Peripheral clock in PMC for TC2 |
| Offset | Field | Description |
|---|---|---|
| 0x0 | TC_CCR | Channel Control Register |
| 0x4 | TC_CMR | Channel Mode Register (Capture Mode / Waveform Mode) |
| 0x10 | TC_CV | Counter Value |
| 0x14 | TC_RA | Register A |
| 0x18 | TC_RB | Register B |
| 0x1C | TC_RC | Register C |
| 0x20 | TC_SR | Status Register |
| 0x24 | TC_IER | Interrupt Enable Register |
| 0x28 | TC_IDR | Interrupt Disable Register |
| 0x2C | TC_IMR | Interrupt Mask Register |
| Function | Description |
|---|---|
| AT91F_TC_GetInterruptMaskStatus | Return TC Interrupt Mask Status |
| AT91F_TC_IsInterruptMasked | Test if TC Interrupt is Masked |
| AT91F_TC_InterruptDisable | Disable TC Interrupt |
| AT91F_TC_InterruptEnable | Enable TC Interrupt |
| Offset | Name | Description |
|---|---|---|
| 0 | TC_CLKEN AT91C_TC_CLKEN | Counter Clock Enable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1. |
| 1 | TC_CLKDIS AT91C_TC_CLKDIS | Counter Clock Disable Command 0 = No effect. 1 = Disables the clock. |
| 2 | TC_SWTRG AT91C_TC_SWTRG | Software Trigger Command 0 = No effect. 1 = A software trigger is performed: the counter is reset and clock is started. |
| Offset | Name | Description | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2..0 | TC_CLKS AT91C_TC_CLKS | Clock Selection
| |||||||||||||||||||||||||||
| 3a | TC_CLKI AT91C_TC_CLKI | Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. | |||||||||||||||||||||||||||
| 5..4 | TC_BURST AT91C_TC_BURST | Burst Signal Selection
| |||||||||||||||||||||||||||
| 6a | TC_LDBSTOP AT91C_TC_LDBSTOP | Counter Clock Stopped with RB Loading 0 = Counter clock is not stopped when RB loading occurs. 1 = Counter clock is stopped when RB loading occurs. | |||||||||||||||||||||||||||
| 7a | TC_LDBDIS AT91C_TC_LDBDIS | Counter Clock Disabled with RB Loading 0 = Counter clock is not disabled when RB loading occurs. 1 = Counter clock is disabled when RB loading occurs. | |||||||||||||||||||||||||||
| 9..8 | TC_ETRGEDG AT91C_TC_ETRGEDG | External Trigger Edge Selection
| |||||||||||||||||||||||||||
| 10a | TC_ABETRG AT91C_TC_ABETRG | TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger. | |||||||||||||||||||||||||||
| 14a | TC_CPCTRG AT91C_TC_CPCTRG | RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock. | |||||||||||||||||||||||||||
| 15a | TC_WAVE AT91C_TC_WAVE | 0 = Capture Mode is enabled. 1 = Capture Mode is disabled (Waveform Mode is enabled). 0 = Waveform Mode is disabled (Capture Mode is enabled). 1 = Waveform Mode is enabled. | |||||||||||||||||||||||||||
| 17..16 | TC_LDRA AT91C_TC_LDRA | RA Loading Selection
| |||||||||||||||||||||||||||
| 19..18 | TC_LDRB AT91C_TC_LDRB | RB Loading Selection
| |||||||||||||||||||||||||||
| 2..0 | TC_CLKS AT91C_TC_CLKS | Clock Selection
| |||||||||||||||||||||||||||
| 3b | TC_CLKI AT91C_TC_CLKI | Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. | |||||||||||||||||||||||||||
| 5..4 | TC_BURST AT91C_TC_BURST | Burst Signal Selection
| |||||||||||||||||||||||||||
| 6b | TC_CPCSTOP AT91C_TC_CPCSTOP | Counter Clock Stopped with RC Compare 0 = Counter clock is not stopped when counter reaches RC. 1 = Counter clock is stopped when counter reaches RC. | |||||||||||||||||||||||||||
| 7b | TC_CPCDIS AT91C_TC_CPCDIS | Counter Clock Disable with RC Compare 0 = Counter clock is not disabled when counter reaches RC. 1 = Counter clock is disabled when counter reaches RC. | |||||||||||||||||||||||||||
| 9..8 | TC_EEVTEDG AT91C_TC_EEVTEDG | External Event Edge Selection
| |||||||||||||||||||||||||||
| 11..10 | TC_EEVT AT91C_TC_EEVT | External Event Selection
| |||||||||||||||||||||||||||
| 12b | TC_ENETRG AT91C_TC_ENETRG | External Event Trigger enable 0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 1 = The external event resets the counter and starts the counter clock. | |||||||||||||||||||||||||||
| 14..13 | TC_WAVESEL AT91C_TC_WAVESEL | Waveform Selection
| |||||||||||||||||||||||||||
| 15b | TC_WAVE AT91C_TC_WAVE | 0 = Capture Mode is enabled. 1 = Capture Mode is disabled (Waveform Mode is enabled). 0 = Waveform Mode is disabled (Capture Mode is enabled). 1 = Waveform Mode is enabled. | |||||||||||||||||||||||||||
| 17..16 | TC_ACPA AT91C_TC_ACPA | RA Compare Effect on TIOA
| |||||||||||||||||||||||||||
| 19..18 | TC_ACPC AT91C_TC_ACPC | RC Compare Effect on TIOA
| |||||||||||||||||||||||||||
| 21..20 | TC_AEEVT AT91C_TC_AEEVT | External Event Effect on TIOA
| |||||||||||||||||||||||||||
| 23..22 | TC_ASWTRG AT91C_TC_ASWTRG | Software Trigger Effect on TIOA
| |||||||||||||||||||||||||||
| 25..24 | TC_BCPB AT91C_TC_BCPB | RB Compare Effect on TIOB
| |||||||||||||||||||||||||||
| 27..26 | TC_BCPC AT91C_TC_BCPC | RC Compare Effect on TIOB
| |||||||||||||||||||||||||||
| 29..28 | TC_BEEVT AT91C_TC_BEEVT | External Event Effect on TIOB
| |||||||||||||||||||||||||||
| 31..30 | TC_BSWTRG AT91C_TC_BSWTRG | Software Trigger Effect on TIOB
|
| Offset | Name | Description |
|---|---|---|
| 0 | TC_COVFS AT91C_TC_COVFS | Counter Overflow 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register. |
| 1 | TC_LOVRS AT91C_TC_LOVRS | Load Overrun 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-tus Register, if WAVE = 0. |
| 2 | TC_CPAS AT91C_TC_CPAS | RA Compare 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1. |
| 3 | TC_CPBS AT91C_TC_CPBS | RB Compare 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1. |
| 4 | TC_CPCS AT91C_TC_CPCS | RC Compare 0 = RC Compare has not occurred since the last read of the Status Register. 1 = RC Compare has occurred since the last read of the Status Register. |
| 5 | TC_LDRAS AT91C_TC_LDRAS | RA Loading 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0. |
| 6 | TC_LDRBS AT91C_TC_LDRBS | RB Loading 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0. |
| 7 | TC_ETRGS AT91C_TC_ETRGS | External Trigger 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register. |
| 16 | TC_CLKSTA AT91C_TC_CLKSTA | Clock Enabling 0 = Clock is disabled. 1 = Clock is enabled. |
| 17 | TC_MTIOA AT91C_TC_MTIOA | TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. |
| 18 | TC_MTIOB AT91C_TC_MTIOB | TIOA Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high. |
| Offset | Name | Description |
|---|---|---|
| 0 | TC_COVFS AT91C_TC_COVFS | Counter Overflow 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register. |
| 1 | TC_LOVRS AT91C_TC_LOVRS | Load Overrun 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-tus Register, if WAVE = 0. |
| 2 | TC_CPAS AT91C_TC_CPAS | RA Compare 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1. |
| 3 | TC_CPBS AT91C_TC_CPBS | RB Compare 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1. |
| 4 | TC_CPCS AT91C_TC_CPCS | RC Compare 0 = RC Compare has not occurred since the last read of the Status Register. 1 = RC Compare has occurred since the last read of the Status Register. |
| 5 | TC_LDRAS AT91C_TC_LDRAS | RA Loading 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0. |
| 6 | TC_LDRBS AT91C_TC_LDRBS | RB Loading 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0. |
| 7 | TC_ETRGS AT91C_TC_ETRGS | External Trigger 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register. |
| Offset | Name | Description |
|---|---|---|
| 0 | TC_COVFS AT91C_TC_COVFS | Counter Overflow 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register. |
| 1 | TC_LOVRS AT91C_TC_LOVRS | Load Overrun 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-tus Register, if WAVE = 0. |
| 2 | TC_CPAS AT91C_TC_CPAS | RA Compare 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1. |
| 3 | TC_CPBS AT91C_TC_CPBS | RB Compare 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1. |
| 4 | TC_CPCS AT91C_TC_CPCS | RC Compare 0 = RC Compare has not occurred since the last read of the Status Register. 1 = RC Compare has occurred since the last read of the Status Register. |
| 5 | TC_LDRAS AT91C_TC_LDRAS | RA Loading 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0. |
| 6 | TC_LDRBS AT91C_TC_LDRBS | RB Loading 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0. |
| 7 | TC_ETRGS AT91C_TC_ETRGS | External Trigger 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register. |
| Offset | Name | Description |
|---|---|---|
| 0 | TC_COVFS AT91C_TC_COVFS | Counter Overflow 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register. |
| 1 | TC_LOVRS AT91C_TC_LOVRS | Load Overrun 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-tus Register, if WAVE = 0. |
| 2 | TC_CPAS AT91C_TC_CPAS | RA Compare 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1. |
| 3 | TC_CPBS AT91C_TC_CPBS | RB Compare 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1. |
| 4 | TC_CPCS AT91C_TC_CPCS | RC Compare 0 = RC Compare has not occurred since the last read of the Status Register. 1 = RC Compare has occurred since the last read of the Status Register. |
| 5 | TC_LDRAS AT91C_TC_LDRAS | RA Loading 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0. |
| 6 | TC_LDRBS AT91C_TC_LDRBS | RB Loading 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0. |
| 7 | TC_ETRGS AT91C_TC_ETRGS | External Trigger 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register. |