| Periph ID AIC | Symbol | Description |
|---|---|---|
| 1 | (AT91C_ID_SYS) | System Interrupt |
| Signal | Symbol | PIO controller | Description |
|---|---|---|---|
| D20 | (AT91C_PC20_D20 ) | PIOC Periph: A Bit: 20 | Data Bus [20] |
| D21 | (AT91C_PC21_D21 ) | PIOC Periph: A Bit: 21 | Data Bus [21] |
| D30 | (AT91C_PC30_D30 ) | PIOC Periph: A Bit: 30 | Data Bus [30] |
| D22 | (AT91C_PC22_D22 ) | PIOC Periph: A Bit: 22 | Data Bus [22] |
| D31 | (AT91C_PC31_D31 ) | PIOC Periph: A Bit: 31 | Data Bus [31] |
| D23 | (AT91C_PC23_D23 ) | PIOC Periph: A Bit: 23 | Data Bus [23] |
| D16 | (AT91C_PC16_D16 ) | PIOC Periph: A Bit: 16 | Data Bus [16] |
| D24 | (AT91C_PC24_D24 ) | PIOC Periph: A Bit: 24 | Data Bus [24] |
| D17 | (AT91C_PC17_D17 ) | PIOC Periph: A Bit: 17 | Data Bus [17] |
| D25 | (AT91C_PC25_D25 ) | PIOC Periph: A Bit: 25 | Data Bus [25] |
| D18 | (AT91C_PC18_D18 ) | PIOC Periph: A Bit: 18 | Data Bus [18] |
| D26 | (AT91C_PC26_D26 ) | PIOC Periph: A Bit: 26 | Data Bus [26] |
| D19 | (AT91C_PC19_D19 ) | PIOC Periph: A Bit: 19 | Data Bus [19] |
| D27 | (AT91C_PC27_D27 ) | PIOC Periph: A Bit: 27 | Data Bus [27] |
| D28 | (AT91C_PC28_D28 ) | PIOC Periph: A Bit: 28 | Data Bus [28] |
| D29 | (AT91C_PC29_D29 ) | PIOC Periph: A Bit: 29 | Data Bus [29] |
| Function | Description |
|---|---|
| AT91F_SDRAMC_CfgPMC | Enable Peripheral clock in PMC for SDRAMC |
| AT91F_SDRAMC_CfgPIO | Configure PIO controllers to drive SDRAMC signals |
| Offset | Field | Description |
|---|---|---|
| 0x0 | SDRAMC_MR | SDRAM Controller Mode Register |
| 0x4 | SDRAMC_TR | SDRAM Controller Refresh Timer Register |
| 0x8 | SDRAMC_CR | SDRAM Controller Configuration Register |
| 0xC | SDRAMC_HSR | SDRAM Controller High Speed Register |
| 0x10 | SDRAMC_LPR | SDRAM Controller Low Power Register |
| 0x14 | SDRAMC_IER | SDRAM Controller Interrupt Enable Register |
| 0x18 | SDRAMC_IDR | SDRAM Controller Interrupt Disable Register |
| 0x1C | SDRAMC_IMR | SDRAM Controller Interrupt Mask Register |
| 0x20 | SDRAMC_ISR | SDRAM Controller Interrupt Mask Register |
| 0x24 | SDRAMC_MDR | SDRAM Memory Device Register |
| Offset | Name | Description | ||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 3..0 | SDRAMC_MODE AT91C_SDRAMC_MODE | Mode 0: Normal Mode 1:Issue a NOP Command 2:Issue a All Banks Precharge Command 3:Issue a Load Mode Register 4:Issue a Refresh
|
| Offset | Name | Description |
|---|---|---|
| 11..0 | SDRAMC_COUNT AT91C_SDRAMC_COUNT | Refresh Counter |
| Offset | Name | Description | |||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1..0 | SDRAMC_NC AT91C_SDRAMC_NC | Number of Column Bits 0: 8. 1: 9. 3: 10. 3: 11.
| |||||||||||||||||||||||||||||||||||||||||||||||||||
| 3..2 | SDRAMC_NR AT91C_SDRAMC_NR | Number of Row Bits 0: 11. 1: 12. 3: 13. 3: Reserved.
| |||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | SDRAMC_NB AT91C_SDRAMC_NB | Number of Banks 0: 2. 1: 4.
| |||||||||||||||||||||||||||||||||||||||||||||||||||
| 6..5 | SDRAMC_CAS AT91C_SDRAMC_CAS | CAS Latency 0: Reserved. 1: Reserved. 2: 2. 3: 3.
| |||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | SDRAMC_DBW AT91C_SDRAMC_DBW | Data Bus Width 0: 32 bits. 1: 16bits.
| |||||||||||||||||||||||||||||||||||||||||||||||||||
| 11..8 | SDRAMC_TWR AT91C_SDRAMC_TWR | Number of Write Recovery Time Cycles
| |||||||||||||||||||||||||||||||||||||||||||||||||||
| 15..12 | SDRAMC_TRC AT91C_SDRAMC_TRC | Number of RAS Cycle Time Cycles
| |||||||||||||||||||||||||||||||||||||||||||||||||||
| 19..16 | SDRAMC_TRP AT91C_SDRAMC_TRP | Number of RAS Precharge Time Cycles
| |||||||||||||||||||||||||||||||||||||||||||||||||||
| 23..20 | SDRAMC_TRCD AT91C_SDRAMC_TRCD | Number of RAS to CAS Delay Cycles
| |||||||||||||||||||||||||||||||||||||||||||||||||||
| 27..24 | SDRAMC_TRAS AT91C_SDRAMC_TRAS | Number of RAS Active Time Cycles
| |||||||||||||||||||||||||||||||||||||||||||||||||||
| 31..28 | SDRAMC_TXSR AT91C_SDRAMC_TXSR | Number of Command Recovery Time Cycles
|
| Offset | Name | Description | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | SDRAMC_DA AT91C_SDRAMC_DA | Decode Cycle Enable Bit
|
| Offset | Name | Description | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1..0 | SDRAMC_LPCB AT91C_SDRAMC_LPCB | Low-power Configurations
| |||||||||||||||
| 6..4 | SDRAMC_PASR AT91C_SDRAMC_PASR | Partial Array Self Refresh (only for Low Power SDRAM) | |||||||||||||||
| 9..8 | SDRAMC_TCSR AT91C_SDRAMC_TCSR | Temperature Compensated Self Refresh (only for Low Power SDRAM) | |||||||||||||||
| 11..10 | SDRAMC_DS AT91C_SDRAMC_DS | Drive Strenght (only for Low Power SDRAM) | |||||||||||||||
| 13..12 | SDRAMC_TIMEOUT AT91C_SDRAMC_TIMEOUT | Time to define when Low Power Mode is enabled
|
| Offset | Name | Description |
|---|---|---|
| 0 | SDRAMC_RES AT91C_SDRAMC_RES | Refresh Error Status |
| Offset | Name | Description |
|---|---|---|
| 0 | SDRAMC_RES AT91C_SDRAMC_RES | Refresh Error Status |
| Offset | Name | Description |
|---|---|---|
| 0 | SDRAMC_RES AT91C_SDRAMC_RES | Refresh Error Status |
| Offset | Name | Description |
|---|---|---|
| 0 | SDRAMC_RES AT91C_SDRAMC_RES | Refresh Error Status |
| Offset | Name | Description | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 1..0 | SDRAMC_MD AT91C_SDRAMC_MD | Memory Device Type
|